The present invention relates to a method and/or architecture for providing flipchip packaging generally and, more particularly, to an enhanced laminate flipchip package using a heatspreader with a high coefficient of thermal expansion (CTE).
Flipchip interconnect technology supports an xe2x80x9carea array interconnect,xe2x80x9d in which a die (circuit) is mechanically and electrically connected through an array of solder bumps on the active face of the circuit. The flipchip technique increases the number of connections that can be made for a given die size and can also improve electrical performance. The die is attached to the substrate face down and can be reinforced with an epoxy underfill.
Referring to FIG. 1, a conventional laminate flipchip package 10 is shown. The flipchip package 10 includes a silicon die 12 attached to a laminate substrate 14 using flipchip solder bumps 16. A gap between the die 12 and the substrate 14 is filled with an underfill 18. A stiffener 20 is attached to the substrate 14 using a high modulus epoxy material 22 to flatten the substrate 14. A heatspreader 24 is attached to (i) the die 12 using a thermally conductive low modulus material 26 such as thermal grease and (ii) the stiffener 20 using a high modulus epoxy material 28. The substrate 14 has solder balls 30 on the side opposite the die 12.
Component and board level reliability of conventional laminate flipchip packages can be a major concern. The die 12 can have a coefficient of thermal expansion (CTE) of approximately 3 ppm/xc2x0 C. The laminate substrate 14 can have a CTE of approximately 17 ppm/xc2x0 C. Because of the difference in expansion between the die 12 and the substrate 14 (i.e., the mismatched CTEs), the solder bumps 16 can fatigue and cause failure. To prevent fatigue of the solder bumps 16, the conventional flipchip package 10 uses a high modulus underfill material 18 (i.e., a modulus in the range of 3 to 10 GPa).
In addition, a mismatch between the CTE of the die 12 and the CTE of the substrate 14 can warp the silicon die 12 causing tensile stress on the back side (non-active side) of the silicon die 12. Tensile stress on the die 12 can lead to cracks in the silicon die 12 during processing and reliability testing. The warpage of the die 12 can contribute significantly to the overall warpage of the package 10. Excess warpage in the region of the substrate 14 attached to the die 12 can cause cracks in the substrate 14 during stress testing. The stiffener 20 is needed to prevent excess warpage of the package 10. Stress generated at the interface between the die 12 and the underfill material 18 due to the CTE mismatch can cause delamination of the underfill material 18 from the die 12. The board level reliability of solder joints formed by the solder balls 30 can be compromised due to a CTE mismatch between the package 10 and the printed circuit board (PCB).
It would be desirable to have a laminate flipchip package that reduces and/or eliminates the component and board level reliability problems due to die and substrate CTE mismatch.
The present invention concerns a flipchip packaged integrated circuit comprising a substrate, a die and a heatspreader. The die may be configured to electrically attach to the substrate. The heat spreader may be rigidly attached to the die. The die and the heatspreader may have a combined coefficient of thermal expansion when attached. The heatspreader may be configured to match the combined coefficient of thermal expansion and a coefficient of thermal expansion of the substrate.
The objects, features and advantages of the present invention include providing a method and/or architecture for an enhanced laminate flipchip package using a high CTE heatspreader that may (i) match the coefficient of thermal expansion (CTE) of the die and heatspreader combination and the CTE of the substrate, (ii) reduce or eliminate underfill material, (iii) reduce or eliminate die cracks, (iv) place the back side of the die in compression, (v) reduce or eliminate substrate warpage in the die region, (vi) reduce or eliminate substrate cracking due to excess warpage in the die region, (vii) make use of an optional stiffener, (viii) reduce stress at the die/underfill interface, (ix) increase the board level reliability of solder joints under the die, and/or (x) increase the component and board level reliability of the flipchip package.